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FEATURES Fully Buffered Inputs and Outputs Fast Channel Switching: 10 ns Internal Current Feedback Output Amplifier High Output Drive: 50 mA Flexible Gain Setting via External Resistor(s) High Speed 250 MHz Bandwidth, G = +2 1000 V/ s Slew Rate Fast Settling Time of 15 ns to 0.1% Low Power: < 10 mA Excellent Video Specifications (RL = 150 , G = +2) Gain Flatness of 0.1 dB Beyond 80 MHz 0.02% Differential Gain Error 0.05 Differential Phase Error Low Crosstalk of -78 dB @ 5 MHz High Disable Isolation of -88 dB @ 5 MHz High Shutdown Isolation of -92 dB @ 5 MHz Low Cost Fast Output Disable Feature for Connecting Multiple Devices (AD8174 Only) Shutdown Feature Reduces Power to 1.5 mA (AD8174 Only) APPLICATIONS Pixel Switching for "Picture-In-Picture" LCD and Plasma Displays Video Routers PRODUCT DESCRIPTION
250 MHz, 10 ns Switching Multiplexers w/Amplifier AD8170/AD8174
FUNCTIONAL BLOCK DIAGRAM
AD8170
SELECT 1 GND 2 -VS 3 IN0 4 +1 +1 LOGIC 8 VOUT 7 -VIN
6 +VS 5 IN1
AD8174
IN0 1 GND 2 IN1 3 GND 4 IN2 5 -VS 6 IN3 7 +1
2
+1
14 +VS 13 VOUT
+1
2
12 -VIN 11 SD LOGIC 10 ENABLE 9 8 A1 A0
+1
-2 -3 -4 -5 -6 -7 -8 -9 1G
NORMALIZED FLATNESS - dB
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1M
RF = 549 (AD8174R) RL = 100
10M 100M FREQUENCY - Hz
Figure 1. Small Signal Frequency Response
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
NORMALIZED OUTPUT - dB
The AD8170(2:1) and AD8174(4:1) are very high speed buffered multiplexers. These multiplexers offer an internal current feedback output amplifier whose gain can be programmed via external resistors and is capable of delivering 50 mA of output current. They offer -3 dB signal bandwidth of 250 MHz and slew rate of greater than 1000 V/s. Additionally, the AD8170 and AD8174 have excellent video specifications with low differential gain and differential phase error of 0.02% and 0.05 and 0.1 dB flatness out to 80 MHz. With a low 78 dB of crosstalk and better than 88 dB isolation, these devices are useful in many high speed applications. These are low power devices consuming only 9.7 mA from a 5 V supply.
The AD8174 offers a high speed disable feature allowing the output to be put into a high impedance state for cascading stages so that the off channels do not load the output bus. Additionally, the AD8174 can be shut down (SD) when not in use to minimize power consumption (IS = 1.5 mA). These products will be offered in 8-lead and 14-lead PDIP and SOIC packages.
0 VIN = 50mV rms G = +2 RF = 499 (AD8170R) -1
(@ T = +25 = AD8170/AD8174-SPECIFICATIONS (AD8170R), R C,=V549
A S F
5 V, RL = 150 , G = +2, RF = 499 (AD8174R) unless otherwise noted)
AD8170A/AD8174A Min Typ Max Units
Parameter SWITCHING CHARACTERISTICS Switching Time1 50% Logic to 10% Output Settling 50% Logic to 90% Output Settling 50% Logic to 99.9% Output Settling ENABLE to Channel ON Time2 (AD8174R) 50% Logic to 90% Output Settling ENABLE to Channel OFF Time2 (AD8174R) 50% Logic to 90% Output Settling Shutdown to Channel ON Time3 (AD8174R) 50% Logic to 90% Output Settling Shutdown to Channel OFF Time3 (AD8174R) 50% Logic to 90% Output Settling Channel Switching Transient (Glitch)4 DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Input Current Logic "0" Input Current DYNAMIC PERFORMANCE -3 dB Bandwidth (Small Signal)5 -3 dB Bandwidth (Large Signal)5 0.1 dB Bandwidth5 Rise and Fall Time (10% to 90%) Slew Rate Settling Time to 0.1% DISTORTION/NOISE PERFORMANCE Differential Gain Differential Phase All Hostile Crosstalk6 AD8170R All Hostile Crosstalk6 Disable Isolation7 Shutdown Isolation8 Input Voltage Noise +Input Current Noise -Input Current Noise Total Harmonic Distortion DC/TRANSFER CHARACTERISTICS Transresistance Open-Loop Voltage Gain Gain Accuracy9 Gain Matching Input Offset Voltage Input Offset Voltage Matching Input Offset Voltage Drift Input Bias Current AD8174R AD8174R AD8174R
Conditions Channel-to-Channel IN0, IN2 = +0.5 V; IN1, IN3 = -0.5 V IN0, IN2 = +0.5 V; IN1, IN3 = -0.5 V IN0, IN2 = +0.5 V; IN1, IN3 = -0.5 V IN0, IN2 = +0.5 V; IN1, IN3 = -0.5 V IN0, IN2 = +0.5 V; IN1, IN3 = -0.5 V IN0, IN2 = +0.5 V; IN1, IN3 = -0.5 V IN0, IN2 = +0.5 V; IN1, IN3 = -0.5 V All Inputs Grounded SELECT, A0, A1, ENABLE, SD Inputs, TMIN-TMAX SELECT, A0, A1, ENABLE, SD Inputs, TMIN-TMAX SELECT, A0, A1 Inputs, TMIN-TMAX ENABLE, SD Inputs, TMIN-TMAX SELECT, A0, A1 Inputs, TMIN-TMAX ENABLE, SD Inputs, TMIN-TMAX VO = 50 mV rms, RL = 100 VO = 1 V rms, RL = 100 VO = 50 mV rms, RF = 499 (AD8170R), RL = 100 VO = 50 mV rms, RF = 549 (AD8174R), RL = 100 2 V Step 2 V Step 2 V Step = 3.58 MHz = 3.58 MHz = 5 MHz, RL = 100 = 30 MHz, RL = 100 = 5 MHz, RL = 100 = 30 MHz, RL = 100 = 5 MHz, RL = 100 = 30 MHz, RL = 100 = 5 MHz, RL = 100 = 30 MHz, RL = 100 = 10 kHz to 30 MHz = 10 kHz to 30 MHz = 10 kHz to 30 MHz C = 10 MHz, VO = 2 V p-p, RL = 150 C = 10 MHz, VO = 2 V p-p, RL = 1 k
7.5 9.1 25 17 120 20 115 138 /104 2.0 50 1 3 30 250 100 85 1.6 1000 15 0.02 0.05 -80 -65 -78 -63 -88 -72 -92 -77 10 1.6 8.5 -60 -72 400 2000 600 6000 0.4 0.05 5 1.5 11 7 3 20 0.8 300 5 5 300
ns ns ns ns ns ns ns mV p-p V V nA A A nA MHz MHz MHz ns V/s ns % Degrees dB dB dB dB dB dB dB dB nV/Hz pA/Hz pA/Hz dBc dBc k V/V % % mV mV mV V/C A A A A nA/C
G = +1, RF = 1 k Channel-to-Channel TMIN to TMAX Channel-to-Channel (+) Switch Input TMIN to TMAX (-) Buffer Input TMIN to TMAX (+) Switch and (-) Buffer Input
9 12 5 15 15 10 14
Input Bias Current Drift
-2-
REV. 0
AD8170/AD8174
Parameter INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Voltage Range Input Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current Output Resistance Output Capacitance POWER SUPPLY Operating Range Power Supply Rejection Ratio Power Supply Rejection Ratio Quiescent Current Conditions (+) Switch Input (-) Buffer Input Channel Enabled (R Package) Channel Disabled (R Package) +CMRR, VCM = 1 V -CMRR, VCM = 1 V RL = 1 k, TMIN-TMAX RL = 150 , TMIN-TMAX RL = 10 Enabled Disabled (AD8174) Disabled (AD8174) 4 58 55 52 50 51 50 4.0 3.5 AD8170A/AD8174A Min Typ Max 1.7 100 1.1 1.1 3.3 56 52 4.26 4.0 50 180 10 10 7.5 6 66 58 8.7/9.7 4.1 1.5 -40 11/13 5 2.5 +85 Units M pF pF V dB dB V V mA mA m M pF V dB dB dB dB mA mA mA C
+PSRR -PSRR
+VS = +4.5 V to +5.5 V, -VS = -5 V TMIN-TMAX -VS = -4.5 V to -5.5 V, +VS= +5 V TMIN-TMAX All Channels "ON", TMIN-TMAX AD8174 Disabled, TMIN-TMAX AD8174 Shutdown, TMIN-TMAX
OPERATING TEMPERATURE RANGE
NOTES 1 Shutdown (SD) and ENABLE pins are grounded (AD8174). IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = -0.5 V dc. SELECT (A0 or A1 for AD8174) input is driven with 0 V to +5 V pulse. Measure transition time from 50% of SELECT (A0 or A1) input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 (or IN2) channel voltage (+0.5 V) to IN1 (or IN3 = -0.5 V) or vice versa. 2 AD8174 only. Shutdown (SD) pin is grounded. ENABLE pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines which channel is activated (i.e., if A0 = Logic 0 and A1 = Logic 1, then IN2 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = -0.5 V dc, and measure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, tOFF is the disable time, tON is the enable time. 3 AD8174 only. ENABLE pin is grounded. Shutdown (SD) pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines which channel is activated (i.e., if A0 = Logic 1 and A1 = Logic O, then IN1 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = -0.5 V dc, and measure transition time from 50% of SD pulse (+2.5 V) to 90% of the total output voltage change. In Fig ure 6, tOFF is the shutdown assert time, tON is the shutdown release time. 4 All inputs are grounded. SELECT (A0 or A1 for AD8174) input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT (A0 or A1) pulse increases the glitch magnitude due to coupling via the ground plane. 5 Bandwidth of the multiplexer is dependent upon the resistor feedback network. Refer to Table III for recommended feedback component values, which give the best compromise between a wide and a flat frequency response. 6 Select input(s) that is (are) not being driven (i.e., if SELECT is Logic 1, activated input is IN1; in AD8174, if A0 = Logic 0, A1 = Logic 1, activated input is IN2). Drive all other inputs with V IN = 0.707 V rms, and monitor output at f = 5 MHz and 30 MHz; RL = 100 (see Figure 13). 7 AD8174 only. Shutdown (SD) pin is grounded. Mux is disabled, (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with V IN = 0.354 V rms. Output is monitored at f = 5 MHz and 30 MHz; R L = 100 . In this mode, the output impedance of the disabled mux is very high (typ 10 M ), and the signal couples across the package; the load impedance and the feedback network determine the crosstalk. For instance, in a closed-loop gain of +1, r OUT 10 M, in a gain of +2 (RF = RG = 549 ), rOUT = 1.1 k (see Figure 14). 8 AD8174 only. ENABLE pin is grounded. Mux is shutdown (i.e., SD = Logic 1), and all inputs are driven simultaneously with V IN = 0.354 V rms. Output is monitored at f = 5 MHz and 30 MHz; RL = 100 . (see Figure 14). The mux output impedance in shutdown mode is the same as the disabled mux output impedance. 9 For Gain Accuracy expression, refer to Equation 4. Specifications subject to change without notice.
Table I. AD8170 Truth Table
SELECT 0 1 VOUT IN0 IN1
Table II. AD8174 Truth Table
A0 0 1 0 1 X X
A1 0 0 1 1 X X
ENABLE 0 0 0 0 1 X
SD 0 0 0 0 0 1
VOUT IN0 IN1 IN2 IN3 HIGH Z, IS = 4.1 mA HIGH Z, IS = 1.5 mA
REV. 0
-3-
AD8170/AD8174
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V Internal Power Dissipation2 AD8170 8-Lead Plastic (N) . . . . . . . . . . . . . . . . . 1.3 Watts AD8170 8-Lead Small Outline (R) . . . . . . . . . . . 0.9 Watts AD8174 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts AD8174 14-Lead Small Outline (R) . . . . . . . . . . 1.0 Watts Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Output Short Circuit Duration . . Observe Power Derating Curves Storage Temperature Range N & R Packages . . . . . . . . . . . . . . . . . . . . -65C to +125C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Pin Plastic Package: JA = 90C/Watt; 8-Pin SOIC Package: JA = 160C/Watt; 14-Pin Plastic Package: JA = 90C/Watt 14-Pin SOIC Package: JA = 120C/Watt, where P D = (TJ-TA)/JA.
The maximum power that can be safely dissipated by the AD8170 and AD8174 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure. While the AD8170 and AD8174 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figures 2 and 3.
2.0
MAXIMUM POWER DISSIPATION - Watts
8-PIN MINI-DIP PACKAGE
TJ = +150C
1.5
ORDERING GUIDE
Model AD8170AN AD8170AR AD8170AR-REEL AD8174AN AD8174AR AD8174AR-REEL AD8170-EB AD8174-EB Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Evaluation Board Evaluation Board Package Description 8-Pin Plastic DIP 8-Pin SOIC Reel 8-Pin SOIC 14-Pin Plastic DIP 14-Pin Narrow SOIC Reel 14-Pin SOIC For AD8170R For AD8174R Package Option N-8 SO-8 SO-8 N-14 R-14 R-14
1.0
8-PIN SOIC PACKAGE 0.5
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE - C
70
80 90
Figure 2. AD8170 Maximum Power Dissipation vs. Temperature
2.5 MAXIMUM POWER DISSIPATION - Watts TJ = +150C
2.0 14-PIN DIP PACKAGE
1.5
14-PIN SOIC 1.0
0.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C
80 90
Figure 3. AD8174 Maximum Power Dissipation vs. Temperature
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8170/AD8174 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. 0
Typical Performance Characteristics - AD8170/AD8174
tFALL = 9.1ns tRISE = 7.5ns
OUTPUT (AD8170R) G = +2 RF = 499 (AD8170R) SEL SWITCHING RF = 549 (AD8174R) RL = 100 A0 SWITCHING
DUT OUT 500mV/DIV
OUTPUT
50mV/DIV
IN0, IN2 = +0.5V IN1, IN3 = +0.5V
G = +2 RF = RG = 499 RL = 100
OUTPUT (AD8174R)
A1 SWITCHING
SELECT PULSE 0 TO +5V
SEL, A0, A1 PULSE 0 TO +5V 10ns/DIV
5ns/DIV
Figure 4. Channel Switching Characteristics
Figure 7. Switching Transient (Glitch) Response
4
AD8174R
INO = +0.5VDC G = +2 RF = 549 RL = 100
VOUT - Volts
3 2 1 0 -1 -2
G = +2 RF = RG = 1k RL = 150
OUTPUT
200mV/DIV
tOFF = 120ns
tON = 17ns ENABLE PULSE 0 TO +5V (5nsec EDGES) 50ns/DIV
-3 -4 -3
-2
-1
0 VIN - Volts
1
2
3
Figure 5. Enable and Disable Switching Characteristics
Figure 8. Output Voltage vs. Input Voltage, G = +2
9 6 VIN = 1.0V rms
9 G = +2 RF = 549 RL = 100 0 -3
INPUT LEVEL - dBV
OUTPUT
AD8174R
3
OUTPUT LEVEL - dBV
INO = +0.5VDC G = +2 RF = 549 RL = 100
200mV/DIV
VIN = 0.5V rms 0 -3 -6 -9 -12 -15 -18 -21 1M VIN = 625mV rms VIN = 125mV rms VIN = 0.25V rms
-6 -9 -12 -15 -18 -21 -24 -27 1G
tON = 20ns tOFF = 115ns SHUTDOWN PULSE 0 TO +5V (5nsec EDGES)
50ns/DIV
10M 100M FREQUENCY - Hz
Figure 6. Shutdown Switching Characteristics
Figure 9. Large Signal Frequency Response
REV. 0
-5-
AD8170/AD8174
-10
G = +2 RF = 499 RF = 549 RL = 100
(AD8170R) (AD8174R)
-20 -30 -40
VIN = +0.707V rms G = +2 RF = 499 (AD8170R) RF = 549 (AD8174R) RL = 100
CROSSTALK - dB
-50 AD8170R -60 -70 -80 -90 AD8174R
20mV/DIV
-100
20ns/DIV
-110 0.1
1M
10M FREQUENCY - Hz
100M
1G
Figure 10. Small Signal Pulse Response
Figure 13. All-Hostile Crosstalk vs. Frequency
-20 VOUT = 4V p-p G = +2 RF = 499 (AD8170R) RF = 549 (AD8174R) RL = 100 -30 -40 -50
ISOLATION - dB
VIN = +0.354V rms G = +2 RF = 549 RL = 100
800mV/DIV
-60 -70 -80 -90 DISABLE ISOLATION
ENABLE = LOGIC 1 SD = LOGIC 0
SD = LOGIC 1 ENABLE = LOGIC 0
-100 -110 10ns/DIV -120 0.03 SHUTDOWN ISOLATION 0.1 1 10 FREQUENCY - MHz 100 500
Figure 11. Large Signal Transient Response
Figure 14. AD8174R Disable and Shutdown Isolation vs. Frequency
VOLTAGE NOISE - nV/Hz
1
2
3
4
5
DIFF PHASE - Degrees
6 IRE
7
8
9
10
11
0.05 0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03
10
VNOISE INVERTING INPUT I
10
SWITCHING INPUT I
1
2
3
4
5
6 IRE
7
8
9
10
11
1 10 100 1k 10k FREQUENCY - Hz 100k 1 1M
Figure 12. Differential Gain and Phase Error
Figure 15. Noise vs. Frequency
-6-
REV. 0
CURRENT NOISE - pA/Hz
0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04
100
100
DIFF GAIN - %
G = +2 RL = 150 RF = 499 (AD8170R) RF = 549 (AD8174R)
AD8170/AD8174
-30 -40
HARMONIC DISTORTION - dB
-50 -60 -70
-2 -3
NORMALIZED FLATNESS - dB
CL = 300pF +0.1 0 -0.1 -0.2 -0.3 -0.4 1M CL = 300pF CL = 100pF CL = 50pF CL = 50pF CL = 100pF
2ND HARMONIC -80 -90 -100 3RD HARMONIC -110 *WORST CHANNEL -120 0.5 1 10 FREQUENCY - MHz 100
-4 -5 -6 -7 -8 -9 1G
10M 100M FREQUENCY - Hz
Figure 16. Harmonic Distortion vs. Frequency
Figure 19. Frequency Response vs. Capacitive Load, G = +2
1M 316k 100k 31.6k DISABLED
IMPEDANCE -
(OR SHUTDOWN) OUTPUT IMPEDANCE 10k (G = +1)
ENABLED (OR DISABLED) INPUT IMPEDANCE
VIN = +0.221V rms G = +2 RF = 499 (AD8170R) RF = 549 (AD8174R)
0 VIN = 50mV rms G = +2 RF = 499 (AD8170R) RF = 549 (AD8174R) RL = 100 -1 -2 -3 -4 -5 -6 -7 -8 -9 1G
NORMALIZED OUTPUT - dB
PHASE - Degrees
3.16k
NORMALIZED FLATNESS - dB
ENABLE, SD = LOGIC 1; G = +1
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1M
ENABLE, SD = LOGIC 1; G = +2 OUTPUT IMPEDANCE (G= +2)
1k DISABLED (OR SHUTDOWN) 316 100 ENABLED OUTPUT IMPEDANCE (G = +2) 31.6 ENABLE, SD = LOGIC 0, RS(OUT) = 50 10 0.03 0.1 1 10 FREQUENCY - MHz 100 500
10M 100M FREQUENCY - Hz
Figure 17. Input & Output Impedance vs. Frequency
Figure 20. Small Signal Frequency Response
0 -10 -20 -30
PSRR - dB
1M
180
TRANSIMPEDANCE -
VIN = 200mV rms G = +2 RF = 499 (AD8170R) RF = 549 (AD8174R) RL = 100
100k TRANSIMPEDANCE PHASE 10k
135
90
-PSRR -40 -50 -60 -70 -80 0.03 +PSRR
1k
45
100
0
0.1
1 10 FREQUENCY - MHz
100
500
10 1k
10k
100k 1M 10M FREQUENCY - Hz
100M
-45 1G
Figure 18. Power Supply Rejection vs. Frequency
Figure 21. Open-Loop Transresistance and Phase vs. Frequency
REV. 0
-7-
NORMALIZED OUTPUT - dB
VOUT = 2V p-p G = +2 RF = 499 (AD8170R) RF = 549 (AD8174R) RL = 100
VOUT = 2V p-p G = +2 RF = 1k RS(OUT) = 20
CL = 20pF CL = 0
0 -1
AD8170/AD8174
THEORY OF OPERATION General
The AD8170/AD8174 multiplexers integrate wideband analog switches with a high speed current feedback amplifier. The input switches are complementary bipolar follower stages that are turned on and off by using a current steering technique that attains switch times of less than 10 ns and ensures low switching transients. The 250 MHz current feedback amplifier provides up to 50 mA of drive current. Overall gain and frequency response are set by external resistors for maximum versatility. Figure 22 is a block diagram of the multiplexer signal chain, with a simplified schematic of an input switch. When the channel is on (i.e., VONB more positive than VREFB, VONT more negative than VREFT), I2 flows through Q1 and Q2, and I3 flows through Q3 and Q4. This biases up Q5 through Q8 to form the unity gain follower. I1 and I4 (the "off" currents) are steered, either to another switch or to the power supply. When the channel turns off, I2 and I3 are steered away while I1 switches over to pull the base of Q8 up to VCLT + 1 VBE (about 2.7 volts from ground reference) and I4 switches over to pull the base of Q5 down to VCLB - 1 VBE (about -2.7 volts away from ground reference). Clamping the bases of the reverse biased output transistors to a low impedance point greatly improves isolation performance. The AD8174 has four switches with outputs wired together and driving the positive input of a current feedback amplifier to form a 4:1 multiplexer. It is designed so that only one channel is on at a time. By bringing ENABLE high, the supply current for the amplifier is shut off. This turns the output of the amplifier into a high impedance, allowing the AD8174 to be used in larger arrays. In practice, the disabled output impedance of the mux will be determined by the amplifier's feedback network.
Bringing SD high shuts off the supply current for all the switches, that some of the logic control circuitry and the amplifier, reducing the quiescent current drain to 1.5 mA. If the ENABLE and SD functions are not to be used, those respective pins must be tied to ground for proper operation. Any unused channel input should also be tied to ground. The AD8170 has two switches driving an amplifier to form a 2:1 multiplexer. No disable or shutdown functions are provided.
DC Performance and Noise Considerations
Figure 23 shows the different contributors to total output offset and noise. Total expected output offset can be calculated using Equation 1 below:
R V OS (out ) = ( I B + x RS ) +V OS 1+ F + ( I B - x RF ) RG
[
]
(1)
RS VIN
SWITCH
BUFFER
IB+/Ien+ VOS/Ven IB-/Ien- RF VOUT RG
Figure 23. DC Errors for Buffered Multiplexer
Equations 2 and 3 below can be used to predict the output voltage noise of the multiplexer for different choices of gains and external resistors. The different contributions to output noise are root-sum-squared to calculate total output noise spectral density in Equation 2. As there is no peaking in the multiplier's noise characteristic, the total peak-to-peak output noise will be accurately predicted using Equation 3.
2
V EN(OUT ) nV / Hz =
(
)(
+ IEN x RS
)( )
2
2 R + V EN 1+ F + I EN - x RF RG
(
)
2
+ 4KT RF + RS
RF RF 1+ R + RG R G G
2
2

(2)
V EN p-p =V EN x f -3 dB x 6.2 x1.26
IN0 IN1 IN2 VOUT
(3)
VFB I1 I3 I6 VREFT VOFFT VREFT VONT Q5 Q3 IN3 Q1 Q4 VCLB Q2 Q7 Q8 Q6
VCLT
VREFB
VONB
VREFB
VOFFB
I2
I4
Figure 22. Block Diagram and Simplified Schematic of the AD8170
-8-
REV. 0
AD8170/AD8174
Equation 4 can be used to calculate expected gain error due to the current feedback amplifier's finite transimpedance and common mode rejection. For low gains and recommended feedback resistors, this will be typically less than 0.4%. For most applications with gain greater than 1, the dominant source of gain error will most likely be the ratio-match of the external resistors. All of the dominant contributors to gain error are associated with the buffer amplifier and external resistors. These do not change as different channels are selected, so channel-to-channel gain match of less than 0.05% is easily attained.
R RT G = 1+ F 1- CMRR RF RG RT + RIN 1+ + RF RG
ACL = Closed Loop Gain CT = Transcapacitance 0.8 pF RF = Feedback Resistor G = Ideal Closed Loop Gain GN = (1 + RF/RG) = Noise Gain RIN = Inverting Terminal Input Resistance 100 The -3 dB bandwidth is determined from this model as:
f -3 dB 1 2 CT ( RF +G N RIN )
This model is typically good to within 15%.
[
]
(4)
Table III. Recommended Component Values
Small Signal Large Signal VOUT = 50 mV rms VOUT = 0.707 V rms Gain RF ( ) RG ( ) -3 dB BW (MHz) -3 dB BW (MHz) AD8170R +1 +2 +10 +20 AD8174R +1 +2 +10 +20 1k 499 499 499 1k 549 499 499 -- 499 54.9 26.3 -- 549 54.9 26.3 710 250 50 27 780 235 50 27 270 290 55 27 270 280 55 27
Ideal Gain
Error Terms
RT = Amplifier Transresistance = 600 k RIN = Amplifier Input Resistance 100 CMRR = Amplifier Common-Mode Rejection -52 dB
Choice of External Resistors
The gain and bandwidth of the multiplexer are determined by the closed-loop gain and bandwidth of the onboard current feedback amplifier. These both may be customized by the external resistor feedback network. Table III shows typical bandwidths at some common closed loop gains for given feedback and gain resistors (RF and RG, respectively). The choice of RF is not critical unless the widest and flattest frequency response must be maintained. The resistors recommended in the table result in the widest 0.1 dB bandwidth with the least peaking. 1% resistors are recommended for applications requiring the best control of bandwidth. Packaging parasitics vary between DIP and SOIC packages, which may result in a slightly different resistor value for optimum frequency performance. Wider bandwidths than those listed in the table can be attained by reducing RF at the expense of increased peaking. To estimate the -3 dB bandwidth for feedback resistors not listed in Table III, the following single-pole model for the current feedback amplifier may be used:
ACL G = 1+ sCT ( RF +GN RIN )
Capacitive Load
The general rule for current feedback amplifiers is that the higher the load capacitance, the higher the feedback resistor required for stable operation. For the best combination of wide bandwidth and clean pulse response, a small output resistor is also recommended, as shown in Figure 24. Table IV contains values of feedback and series resistors that result in the best pulse response for a given load capacitance.
RF +VS RG 0.1F BUFFER VIN 0.1F RT 50 SWITCH -VS 10F CL RS(OUT) VOUT (TO FET PROBE) 10F
Figure 24. Circuit for Driving a Capacitive Load
Table IV. Recommended Feedback and Series Resistors and Bandwidth vs. Capacitive Load and Gain
CL (pF) 20 50 100 300
RF () 1k 1k 2k 2k
G = +1 VOUT = 2 V p-p RSOUT -3 dB BW () (MHz) 50 30 20 20 149 104 73 27
RF () 1k 1k 1k 1k
G = +2 VOUT = 2 V p-p RSOUT -3 dB BW () (MHz) 20 15 15 15 174 117 80 34
RF () 499 1k 1k 1k
G = +3 VOUT = 2 V p-p RSOUT -3 dB BW () (MHz) 25 15 15 15 170 98 71 33
G RF () 499 499 499 499
+4 RSOUT () 20 20 15 15
REV. 0
-9-
AD8170/AD8174
VOUT = 2V p-p G = +2 RF = 499 (AD8170R) RF = 549 (AD8174R) CL = 300PF RS(OUT) = 15 500mV/DIV OUTPUT VOUT = 1V
INPUT VIN = 0.5V
20ns/DIV
Figure 25. Pulse Response Driving a Large Load Capacitor, CL = 300 pF
Overload Behavior and Recovery
There are three important overload conditions: input voltage overdrive, output voltage overdrive and current overload at the amplifier's negative feedback input. At a gain of 1, recovery from driving the input voltages beyond the voltage range of the input switches is very quick, typically less than 30 ns. Recovery from output overdrive is somewhat slower and depends on how much the output is overdriven. Recovery from 15% overdrive is under 60 ns. 50% overdrive produces recovery times of about 85 ns. Input overdrive in a high gain application can result in a large current flow in the input stage. This current is internally limited to 40 mA. The effect on total power dissipation should be taken into account.
LAYOUT CONSIDERATIONS:
Signal traces should be as short as possible. Stripline or microstrip techniques should be used for long signal traces (longer than about 1 inch). These should be designed with a characteristic impedance of 50 or 75 and be properly terminated at each end using surface mount components. Careful layout is imperative to minimize crosstalk. Guards (ground or supply traces) must be run between all signal traces to limit direct capacitive coupling. Input and output signal lines should fan out away from the mux as much as possible. If multiple signal layers are available, a buried stripline structure having ground plane above, below, and between signal traces will have the best crosstalk performance. Return currents flowing through termination resistors can also increase crosstalk if these currents flow in sections of the finiteimpedance ground circuit that is shared between more than one input or output. Minimizing the inductance and resistance of the ground plane can reduce this effect, but further care should be taken in positioning the terminations. Terminating cables directly at the connectors will minimize the return current flowing on the board, but the signal trace between the connector and the mux will look like an open stub and will degrade the frequency response. Moving the termination resistors close to the input pins will improve the frequency response, but the terminations from neighboring inputs should not have a common ground return.
APPLICATIONS 8-to-1 Video Multiplexer
Realizing the high speed performance attainable with the AD8170 and AD8174 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic component selection are mandatory. Wire wrap boards, prototype boards, and sockets are not recommended because of their high parasitic inductance and capacitance. Instead, surface-mount components should be soldered directly to a printed circuit board (PCB). The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near input and output pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing. One end of the capacitor should be connected to the ground plane and the other within 1/4 inch of each power pin. An additional large (4.7 F-10 F) tantalum capacitor should be connected in parallel with each of the smaller capacitors for low impedance supply bypassing over a broad range of frequencies.
Two AD8174 4-to-1 multiplexers can be combined with a single digital inverter to yield an 8-to-1 multiplexer as shown in Figure 26. The ENABLE control pin allows the two op amp outputs to be connected together directly. Taking the ENABLE pin high shuts off the supply current to the output op amp and places the op amp's output and inverting input (Pin 12, -VIN) in high impedance states. The two least significant bits (LSBs) of the address lines connect directly to the A0 and A1 inputs of both AD8174 devices. The third address line connects directly to the ENABLE input on one device and is inverted before being applied to the ENABLE input on the second device. As a result, when one device is enabled, the second device presents a high impedance. The op amp of the enabled device must however drive both feedback networks ((549 + 549 )/2). The gain of this multiplexer has been set to +2 in this example. This gives an overall gain of +1 when back terminated lines are used. In applications where switching and settling times are critical, the digital control pins (A0, A1 and ENABLE) should also be appropriately terminated (with either 50 or 75 ).
-10-
REV. 0
AD8170/AD8174
+ IN0 75 1 IN1 75 3 IN2 75 0.1F -5V + 10F IN3 75 A0 + IN4 75 1 IN5 75 3 IN6 75 0.1F -5V + 10F IN7 75 +1
2
AD8174
+1 +VS 14 13 12
2
10F 0.1F +5V RBT 75 VOUT 549 SD +5V A2 RT* 549
2 GND +1
4 GND 5 +1
11 LOGIC 10 9 8
ENABLE A1 A0
6 -VS 7 +1
2
A1 RT*
RT*
AD8174
+1 +VS 14 13 12 11 LOGIC 10 9 8 SD 2 GND
10F 0.1F +5V
549 +5V
549
4 GND 5 +1
ENABLE A1 A0
6 -VS 7 +1
2
*OPTIONAL
Figure 26. 8-to-1 Multiplexer
Color Document Scanner
Charge Coupled Devices (CCDs) find widespread use in scanner applications. A monochrome CCD delivers a serial stream of voltage levels, each level being proportional to the light shining on that cell. In the case of the color image scanner shown, there are three output streams, representing red, green and blue. Interlaced with the stream of voltage levels is a voltage representing the reset level (or black level) of each cell. A Correlated Double Sampler (CDS) subtracts these two voltages from each other in order to eliminate the relatively large offsets which are common with CCDs. The next step in the data acquisition process involves digitizing the three signal streams. Assuming that the analog to digital converter chosen has a fast enough sample rate, multiplexing the three streams into a single ADC is generally more economic than using one ADC per channel. In the example shown, the AD8174 is used to multiplex the red, green and blue channels into the AD876, an 8- or 10-bit 20 MSPS ADC. Because of its high bandwidth, the AD8174 is capable of driving the switched capacitor input stage of the AD876 without additional buffering. In addition to the bandwidth, it is necessary to consider the settling time of the multiplexer. In this case, the ADC has a sample rate of 20 MHz which corresponds to a sampling period of 50 ns. Typically, one phase of the sampling clock is used for conversion (i.e., all levels are held steady) and the other
phase is used for switching and settling to the next channel. Assuming a 50% duty cycle, the signal chain must settle within 25 ns. With a settling time to 0.1% of 15 ns, the multiplexer easily satisfies this criterion. In the example shown, the fourth (spare) channel of the AD8174 is used to measure a reference voltage. This voltage would probably be measured less frequently than the R, G and B signals. Multiplexing a reference voltage offers the advantage that any temperature drift effects caused by the multiplexer will equally impact the reference voltage and the to-be-measured signals. If the fourth channel is unused, it is good design practice to tie the input permanently to ground.
CONTROL AND TIMING
A0 A1 SD ENABLE
R
CDS IN0
CCD
G
CDS
AD8174
IN1 VOUT CDS REFERENCE IN2 IN3 -VIN 1k (G = +1) AD876 8/10-BIT 20MSPS A/D
B
Figure 27. Color Document Scanner
REV. 0
-11-
AD8170/AD8174
EVALUATION BOARD
Evaluation boards for the AD8170 and AD8174 are available that have been carefully laid out and tested to demonstrate the specified high speed performance of the devices. Figure 28 and Figure 32 show the schematics of the AD8170 and AD8174 evaluation boards respectively. For ordering information, please refer to the Ordering Guide. Figure 29 shows the silkscreen of the component side of the solder side of the AD8170 evaluation board. Figures 30 and 31 show the layout of the component side and solder side respectively. The silkscreens and layout of the AD8174 evaluation board are shown in Figures 33, 34, 35 and 36.
Both evaluation boards ship with 75 termination resistors on their analog inputs and analog outputs. To use the evaluation board in nonvideo applications where 50 termination is more popular, these resistors can be replaced with 50 values. The digital control pins are terminated with 50 resistors to allow easy connection to laboratory equipment. The gain of the output current feedback op amp on both boards has been set to +2. For other gains the two gain resistors can be easily replaced. Refer to Table III for appropriate values at gains other than +2. For connection to external instruments, side-launched SMA type connectors are provided. Space is also provided on the board for the installation of SMB of SMC type connectors.
R6 75 VOUT
SELECT 1 C1 10F -VS + C2 0.1F R2 75 IN1 R3 75 GND 2 3 -VS 4 +1 LOGIC R1 50
AD8170
8 7 +VS 6 +1 5 C4 0.1F C3 10F + +VS
R5 549 R4 549
IN0
Figure 28. AD8170 Evaluation Board
Figure 29. AD8170 Component Side Silkscreen
Figure 30. AD8170 Board Layout (Component Side)
Figure 31. AD8170 Board Layout (Solder Side)
-12-
REV. 0
AD8170/AD8174
IN0 R1 75 IN1 R2 75 IN2 R3 75 -VS C1 10F + C2 0.1F IN3 R4 75 A0 R5 50 A1 R6 50 R7 50
AD8174
1 +1 +VS 14 13 12
2
C4 0.1F
C3 10F +VS R11 75 VOUT R10 549 R9 549
2 GND 3 +1
4 GND 5 +1
11 LOGIC 10 9 8
6 -VS 7 +1
2
SD R8 50 ENABLE
Figure 32. AD8174 Evaluation Board
Figure 33. AD8174 Component Side Silkscreen
Figure 35. AD8174 Solder Side Silkscreen
Figure 34. AD8174 Board Layout (Component Side)
Figure 36. AD8174 Board Layout (Solder Side)
REV. 0
-13-
AD8170/AD8174
NOTES
1. AD8170R/AD8174R Evaluation Board inputs are configured with 50 impedance striplines. This FR4 board type has the following stripline dimensions: 60-mil width, 12-mil gap between center conductor and outside ground plane "islands," and 62-mil board thickness. 2. Several types of SMA connectors can be mounted on this board: the side-mount type, which can be easily installed at the edges of the board; and the top-mount type, which is placed on top. When using the top-mount SMA connector, it is recommended that the stripline on the outside 1/8" of the board edge be removed with an X-Acto blade as this unused stripline acts as an open stub, which could degrade the smallsignal frequency response of the mux.
3. Input termination resistor placement on the evaluation board is critical to reducing crosstalk. Each termination resistor is oriented so that ground return currents flow counterclockwise to a ground plane "island." Although the direction of this ground current flow is arbitrary, it is important that no two input or output termination resistors share a connection to the same ground "island."
-14-
REV. 0
AD8170/AD8174
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.430 (10.92) 0.348 (8.84)
8 5
14-Lead Plastic DIP (N-14)
0.795 (20.19) 0.725 (18.42)
14 8 7
0.280 (7.11) 0.240 (6.10)
1 4
1
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93)
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC
0.015 (0.381) 0.008 (0.204)
0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC
SEATING PLANE
0.015 (0.381) 0.008 (0.204)
8-Lead Plastic SOIC (SO-8)
14-Lead SOIC (R-14)
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
0.3444 (8.75) 0.3367 (8.55)
14 1 8 7
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
SEATING PLANE
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC
0.0098 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
REV. 0
-15-
-16-
C2205-9-10/96
PRINTED IN U.S.A.

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